In the field of test and measurement, an acquisition device typically collects sample data from one or more electrical test points over some period of time, whereby the value of a sample represents the voltage level of the given test point at a specific point in that timeline. Samples collected in one time-contiguous sequence are commonly considered as a single acquisition. Common tools in this field today include logic analyzers and digital storage oscilloscopes, such as those manufactured by Agilent Technologies, Tektronix Inc. and LeCroy Corp.
Several features of the acquisition devices define their overall performance capabilities. First is the achievable sample rate. Higher rates allow more accurate sampling of the fast electrical signals. Second, is the acquisition device's memory depth, which determines the amount of data that can be collected during an acquisition and thus the duration of time-contiguous samples that can be gathered at once. The third is the rate at which collected data can be transferred to the rest of the acquisition system for processing and display to a user. A shorter cycle time for transferring the desired data from the acquisition device's memory and displaying it to the user provided for less down time between acquisitions, reduces delays for the user, and lessens the chance that events of interest on the unit under test are missed.
Acquisition systems typically have a host processing and display platform such as a dedicated hardware platform or an attached personal computer coupled to the logic analyzer, MSO, or digital storage oscilloscope, operating in accordance with software that can collect, store, and manipulate the data representing sample data over one or more signal channels, and renders such to the user.
Such acquisition device have logical elements which sample each input data signal received, FPGA chips have been designed with input/output registers for sampling data, such as the Virtex-4 family FPGA from Xilinx, Inc. Such an FPGA, once programmed, is part of the electronics of the acquisition device for storing data in memory. By design, the Virtex-4 family FPGA is configurable to acquire data rates as high as 1 Gigasamples per second (GS/s) using a 500 MHz clock. However, it would be desirable if such an FPGA could provide higher data rate sampling than 1 GS/s to improve performance without the need for a more expensive FPGA or specialized logical circuitry which typically requires use of higher clock speeds and logical elements capable to operating at such speeds.
One drawback of viewing high rate signals is that readout, processing, and display of such high rate data is difficult with communication bandwidth bottlenecks between the acquisition device and the host computer system and hardware limitations of the host computer system. Accordingly, it would be advantageous if a high rate signal was compressed at the acquisition device in its memory to facilitate readout to the host computer system, while at the same time storing the sampled data, such that both high and low resolutions of the same sampled data acquired at the same time are retained.
Each acquisition device is predefined in much of its function by its FPGA configuration, which is typically set at the time of manufacture of the acquisition device. Accordingly, different models or types of acquisition devices are necessary to achieve different acquisition functions or feature-sets. Thus, it would also be desirable if the acquisition device could be configurable by the attached computer, imperceptibly to the user of the device, thereby avoiding the need for different types of acquisition devices.